MIT 6.004 Computation Structures, Spring 2017

• 1.2.1 What is Information?
• 1.2.2 Quantifying Information
• 1.2.3 Entropy
• 1.2.4 Encoding
• 1.2.5 Fixed-length Encodings
• 1.2.6 Signed Integers: 2's complement
• 1.2.7 Variable-length Encoding
• 1.2.8 Huffman's Algorithm
• 1.2.9 Huffman Code
• 1.2.10 Error Detection and Correction
• 1.2.11 Error Correction
• 1.2.12 Worked Examples: Quantifying Information
• 1.2.12 Worked Examples: Two's Complement Representation
• 1.2.12 Worked Examples: Two's Complement Addition
• 1.2.12 Worked Examples: Huffman Encoding
• 1.2.12 Worked Examples: Error Correction
• 2.2.1 Concrete Encoding of Information
• 2.2.2 Analog Signaling
• 2.2.3 Using Voltages Digitally
• 2.2.4 Combinational Devices
• 2.2.5 Dealing with Noise
• 2.2.6 Voltage Transfer Characteristic
• 2.2.7 VTC Example
• 2.2.8 Worked Examples: The Static Discipline
• 3.2.1 MOSFET: Physical View
• 3.2.2 MOSFET: Electrical View
• 3.2.3 CMOS Recipe
• 3.2.4 Beyond Inverters
• 3.2.5 CMOS Gates
• 3.2.6 CMOS Timing
• 3.2.7 Lenient Gates
• 3.2.8 Worked Examples: CMOS Functions
• 3.2.8 Worked Examples: CMOS Logic Gates
• 4.2.1 Sum of Products
• 4.2.2 Useful Logic Gates
• 4.2.3 Inverting Logic
• 4.2.4 Logic Simplification
• 4.2.5 Karnaugh Maps
• 4.2.6 Multiplexers
• 4.2.7 Read-only Memories
• 4.2.8 Worked Examples: Truth Tables
• 4.2.8 Worked Examples: Gates and Boolean Logic
• 4.2.8 Worked Examples: Combinational Logic Timing
• 4.2.8 Worked Examples: Karnaugh Maps
• 5.2.1 Digital State
• 5.2.2 D Latch
• 5.2.3 D Register
• 5.2.4 D Register Timing
• 5.2.5 Sequential Circuit Timing
• 5.2.6 Timing Example
• 5.2.7 Worked Example 1
• 5.2.8 Worked Example 2
• 6.2.1 Finite State Machines
• 6.2.2 State Transition Diagrams
• 6.2.3 FSM States
• 6.2.4 Roboant Example
• 6.2.5 Equivalent States; Implementation
• 6.2.6 Synchronization and Metastability
• 6.2.7 Worked Examples: FSM States and Transitions
• 6.2.7 Worked Examples: FSM Implementation
• 7.2.1 Latency and Throughput
• 7.2.2 Pipelined Circuits
• 7.2.3 Pipelining Methodology
• 7.2.4 Circuit Interleaving
• 7.2.5 Self-timed Circuits
• 7.2.6 Control Structures
• 7.2.7 Worked Examples: Pipelining
• 7.2.7 Worked Examples: Pipelining 2
• 8.2.1 Power Dissipation
• 8.2.2 Carry-select Adders
• 8.2.3 Carry-lookahead Adders
• 8.2.4 Binary Multiplication
• 8.2.5 Multiplier Tradeoffs
• 8.2.6 Part 1 Wrap-up
• 9.2.1 Datapaths and FSMs
• 9.2.2 Programmable Datapaths
• 9.2.3 The von Neumann Model
• 9.2.4 Storage
• 9.2.5 ALU Instructions
• 9.2.6 Constant Operands
• 9.2.7 Memory Access
• 9.2.8 Branches
• 9.2.9 Jumps
• 9.2.10 Worked Examples: Programmable Architectures
• 10.2.1 Intro to Assembly Language
• 10.2.2 Symbols and Labels
• 10.2.3 Instruction Macros
• 10.2.4 Assembly Wrap-up
• 10.2.5 Models of Computation
• 10.2.6 Computability, Universality
• 10.2.7 Uncomputable Functions
• 10.2.8 Worked Examples: Beta Assembly
• 11.2.1 Iterpretation and Compilation
• 11.2.2 Compiling Expressions
• 11.2.3 Compiling Statements
• 11.2.4 Compiler Frontend
• 11.2.5 Optimization and Code Generation
• 11.2.6 Worked Examples
• 12.2.1 Procedures
• 12.2.2 Activation Records and Stacks
• 12.2.3 Stack Frame Organization
• 12.2.4 Compiling a Procedure
• 12.2.5 Stack Detective
• 12.2.6 Worked Examples: Procedures and Stacks
• 13.2.1 Building Blocks
• 13.2.2 ALU Instructions
• 13.2.3 Load and Store
• 13.2.4 Jumps and Branches
• 13.2.5 Exceptions
• 13.2.6 Summary
• 13.2.7 Worked Examples: A Better Beta
• 13.2.7 Worked Examples: Beta Control Signals
• 14.2.1 Memory Technologies
• 14.2.2 SRAM
• 14.2.3 DRAM
• 14.2.4 Non-volatile Storage; Using the Hierarchy
• 14.2.5 The Locality Principle
• 14.2.6 Caches
• 14.2.7 Direct-mapped Caches
• 14.2.8 Block Size; Cache Conflicts
• 14.2.9 Associative Caches
• 14.2.10 Write Strategies
• 14.2.11 Worked Examples: Cache Benefits
• 14.2.11 Worked Examples: Caches
• 15.2.1 Improving Beta Performance
• 15.2.2 Basic 5-Stage Pipeline
• 15.2.3 Data Hazards
• 15.2.4 Control Hazards
• 15.2.5 Exceptions and Interrupts
• 15.2.6 Pipelining Summary
• 15.2.7 Worked Examples: Pipelined Beta
• 15.2.7 Worked Examples: Beta Junkyard
• 16.2.1 Even More Memory Hierarchy
• 16.2.2 Basics of Virtual Memory
• 16.2.3 Page Faults
• 16.2.4 Building the MMU
• 16.2.5 Contexts
• 16.2.6 MMU Improvements
• 16.2.7 Worked Examples: Virtual Memory
• 17.2.1 Recap: Virtual Memory
• 17.2.2 Processes
• 17.2.3 Timesharing
• 17.2.4 Handling Illegal Instructions
• 17.2.5 Supevisor Calls
• 17.2.6 Worked Examples: Operating Systems
• 18.2.1 OS Device Handlers
• 18.2.2 SVCs for Input/Output
• 18.2.3 Example: Match Handler with OS
• 18.2.4 Real Time
• 18.2.5 Weak Priorities
• 18.2.6 Strong Priorities
• 18.2.7 Example: Priorities in Action!
• 18.2.8 Worked Examples: Devices and Interrupts
• 19.2.1 Interprocess Communication
• 19.2.2 Semaphores
• 19.2.3 Atomic Transactions
• 19.2.4 Semaphore Implementation
• 19.2.5 Deadlock
• 19.2.6 Worked Examples: Semaphores
• 20.2.1 System-level Interfaces
• 20.2.2 Wires
• 20.2.3 Buses
• 20.2.4 Point-to-point Communication
• 20.2.5 System-level Interconnect
• 20.2.6 Communication Topologies
• 21.2.1 Instruction-level Parallelism
• 21.2.2 Data-level Parallelism
• 21.2.3 Thread-level Parallelism
• 21.2.4 Shared Memory & Caches
• 21.2.5 Cache Coherence
• 21.2.6 6.004 Wrap-up
• An Interview with Christopher Terman on Teaching Computation Structures